1. Field of the Invention
This invention is related to the field of multiplier circuits in processors.
2. Description of the Related Art
Processors continue to be designed for operation at increasing clock frequencies. As the frequency of operation increases, the power consumption of the processors becomes a larger issue.
One function that processors are typically designed to perform is multiplication. That is, many instruction sets include instructions that cause a multiplication of the operands of the instruction, and so the processors include hardware to perform the multiplication (i.e. a multiplier). As clock frequencies have increased, the multiplier has been pipelined to provide for operation at the desired clock frequency while still maintaining a throughput of one multiply per clock cycle.
Unfortunately, pipelining the multiplier may lead to increased power consumption in the multiplier. For example, many multipliers are designed to perform multiplication using Booth encoding. In Booth encoding, a relatively large number of partial products are generated and then summed to produce the multiplication result. If the multiplier is pipelined, the partial products may have to be captured (e.g. in a latch) to provide a stable input to the next stage in the multiplier pipeline. Since there is a large number of partial products, the number of latches is large. Latches generally consume larger amounts of power, due to their clocked nature, than non-clocked circuits such as logic gates. The power consumption in the relatively large number of latches may thus be a significant component of the power consumed in the multiplier. Additionally, in some cases, the latency added by the latches may increase the latency of the multiplication, which may reduce performance.